Prior Art FIG. 1 shows a general example of a semiconductor device 100. The semiconductor device 100 has a substrate 105 with a back side metal layer 110, a first epitaxial layer 115, and a second epitaxial layer 120. A number of active regions 125 are disposed in the second epitaxial region 120. The active regions 125 contain circuit elements such as transistors or diodes that conduct electric current and dissipate heat. Examples of transistors are bipolar junction transistors (BJTs), metal-oxide field effect transistors (MOSFETs), and junction field effect transistors (JFETs).
The back side metal layer is commonly used to provide an electrical contact (e.g., ground) to the substrate 105 and to provide a solderable surface for mounting the device. For the semiconductor device 100, there is a thermal/electrical resistance R associated with the substrate 105. For vertical power devices such as field effect transistors (FETs) that utilize layer 110 as a source contact, the resistance R can be a significant fraction of the device on resistance Rds-on.
The resistance R can be reduced by reducing the thickness of the substrate 105. However, wafer handling considerations and electrical requirements limit the reduction in thickness that may be applied to the substrate 105 and epitaxial layer 115.
Prior Art FIG. 2A shows an example of a complementary metal-oxide semiconductor (CMOS) inverter circuit 200 fabricated on a p-type substrate 205. A p-channel field effect transistor (PFET) 215 resides in an N-well 210 and is coupled to an n-channel field effect (NFET) transistor 220. The CMOS inverter circuit 200 is a basic building block for digital logic circuits.
Prior Art FIG. 2B shows an equivalent circuit 201 that includes parasitic bipolar transistors Q1 and Q2 that are derived from the p-n junctions associated with the inverter circuit 200. During normal operation of the inverter 200 the parasitic transistors Q1 and Q2 are off. However, if a transient voltage spike or other event produces a large current through Rsubstrate, the voltage drop across Rsubstrate will be sufficient to turn on Q2 and cause a current flow through Rwell. If the voltage drop across Rwell is large enough to turn on Q1, latchup occurs wherein a self sustained low resistance path between Vdd and GND is produced.
FIG. 2C shows 2C shows a schematic representation 202 of the substrate bulk resistance Rsubstrate associated with the equivalent circuit 201 of FIG. 2B. The bulk resistance Rsubstrate is distributed in the region between the N-well 210 and the NFET 220. In contrast to the resistance R of a vertical device, the resistance Rsubstrate is part of a lateral current path.
Thus, in conventional semiconductor substrates there is frequently a bulk region that either contributes to undesirable resistance in operational electrical or thermal paths, or provides an additional current path with undesirable properties.